I’m Jiuyang Liu, a PhD student in Huazhong University of Sicence and Technology(HUST). Main research area contains

  • Logic synthesis framework and algorithm.
  • Advance hardware description language.
  • Hardware verification methodology.
  • SoC framework and architecture
    • memory coherence
    • memory ordering
  • Computer architecture based on RISC-V.

I write Scala, I develop circuits with Chisel, I play tricks on netlist with FIRRTL, I make SoC with RocketChip, and my next project is a type-safe “RocketChip next-generation” SoC.
I’m a research counselor at StarFive, providing uncore solution based on RocketChip, cooperating with guys who are devoted to Chisel, and making uncore cache and RISC-V core.

Education background


  • High performance laser interferometric ranging simulation (2014 - 2016)
  • STT-MTJ memory design (2017)
  • Entrepreneurship - High performance BitCoin miner(2018 - 2019)
    • Chip Architect
      • Design with Chisel3
      • Custom optimization with FIRRTL transform.
      • Full custom design on the critical block.
      • Successfully tapeout with UMC28HPC(2018), SMIC14(2019)
    • System Architect
      • Zynq based FPGA high performance controller.
      • Rust based high performance driver.
  • Consulting(2019 - now)
    • TileLink based bus interconnect solution.
    • Exclusive System Cache with TileLink.
    • Multi-Threaded RISC-V core.
  • Chisel/FIRRTL/RocketChip(2020 - now)
    • cooperate with SiFive CAAT(Chisel and Additional Technology) team working on improving Chisel3, FIRRTL and RocketChip.


  • Scala(skillful)
  • Chisel(skillful)
  • Python(skillful)
  • Z3(know a little about)
  • Rust(know a little about)
  • C++(used to be skillful)
  • Matlab(used to be skillful)
  • Fortran(used to be skillful)


Contact me at [email protected]